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Freescale Semiconductor Data Sheet: Technical Data
Document Number: MC9S08JS16 Rev. 4, 4/2009
MC9S08JS16
MC9S08JS16 Series
Covers: MC9S08JS16 MC9S08JS8 MC9S08JS16L MC9S08JS8L
Features: * 8-Bit HCS08 Central Processor Unit (CPU) - 48 MHz HCS08 CPU (central processor unit) - 24 MHz internal bus frequency - Support for up to 32 interrupt/reset sources * Memory Options - Up to 16 KB of on-chip in-circuit programmable flash memory with block protection and security options - Up to 512 bytes of on-chip RAM - 256 bytes of USB RAM * Clock Source Options - Clock source options include crystal, resonator, external clock - MCG (multi-purpose clock generator) -- PLL and FLL; internal reference clock with trim adjustment * System Protection - Optional computer operating properly (COP) reset with option to run from independent 1 kHz internal clock source or the bus clock - Low-voltage detection - Illegal opcode detection with reset - Illegal address detection with reset * Power-Saving Modes - Wait plus two stops * USB Bootload - Mass erase entire flash array - Partial erase flash array -- erase all flash blocks except for the first 1 KB of flash - Program flash * Peripherals - USB -- USB 2.0 full-speed (12 Mbps) with dedicated on-chip 3.3 V regulator and transceiver; supports endpoint 0 and up to 6 additional endpoints
TBD
20 W-SOIC Case 751D
24 QFN Case 1982-01
- SPI -- One 8- or 16-bit selectable serial peripheral interface module with a receive data buffer hardware match function - SCI -- One serial communications interface module with optional 13 bit break. Full duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wakeup on active edge - MTIM -- One 8-bit modulo counter with 8-bit prescaler and overflow interrupt - TPM -- One 2-channel 16-bit timer/pulse-width modulator (TPM) module; selectable input capture, output compare, and edge-aligned PWM capability on each channel; timer module may be configured for buffered, centered PWM (CPWM) on all channels - KBI -- 8-pin keyboard interrupt module - RTC -- Real-time counter with binary- or decimal-based prescaler - CRC -- Hardware CRC generator circuit using 16-bit shift register; CRC16-CCITT compliancy with x16+x12+x5+1 polynomial * Input/Output - Software selectable pullups on ports when used as inputs - Software selectable slew rate control on ports when used as outputs - Software selectable drive strength on ports when used as outputs - Master reset pin and power-on reset (POR) - Internal pullup on RESET, IRQ, and BKGD/MS pins to reduce customer system cost * Package Options - 24-pin quad flat no-lead (QFN) - 20-pin small outline IC package (SOIC)
This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. (c) Freescale Semiconductor, Inc., 2008-2009. All rights reserved.
Table of Contents
1 2 3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . .6 3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .6 3.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .7 3.4 Electrostatic Discharge (ESD) Protection Characteristics8 3.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .15 3.7 External Oscillator (XOSC) Characteristics . . . . . . . . .17 3.8 MCG Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .18 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.2 Timer/PWM (TPM) Module Timing. . . . . . . . . . 3.10 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12 USB Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 19 19 20 21 24 25 26 26 26
4
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Revision Date Description of Changes
1 2 3 4
9/1/2008 1/8/2009 3/9/2009 4/24/2009
Initial public released In Table 7, changed the parameter description of RIDD and S3IDD, the typicals of RIDD were changed as well. Corrected the 24-pin QFN case number and doc. number information. Added new parts information about MC9S08JS16L and MC9S08JS8L.
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual
(MC9S08JS16RM) Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information.
MC9S08JS16 Series MCU Data Sheet, Rev. 4 2 Freescale Semiconductor
MCU Block Diagram
1
MCU Block Diagram
ON-CHIP ICE AND DEBUG MODULE (DBG) FULL SPEED USB USB ENDPOINT TRANSCEIVER RAM USB MODULE
The block diagram, Figure 1, shows the structure of the MC9S08JS16 series MCU.
HCS08 CORE
USBDP USBDN
BKGD/MS
BDC
CPU
PTA0/KBIP0/TPMCH0 PTA1/KBIP1/MISO
RESET
HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT
8-BIT KEYBOARD INTERRUPT MODULE (KBI)
KBIPx 8 PTA2/KBIP2/MOSI PORT A MISO PTA3/KBIP3/SPSCK PTA4/KBIP4/SS PTA5/KBIP5/TPMCH1 PTA6/KBIP6/RxD PTA7/KBIP7/TxD TPMCH0
IRQ
8-/16-BIT COP IRQ LVD SERIAL PERIPHERAL INTERFACE MODULE (SPI)
MOSI SPSCK SS RxD TxD
USER FLASH (IN BYTES) MC9S08JS16 = 16,384 MC9S08JS16L = 16,384 MC9S08JS8 = 8,192 MC9S08JS8L = 8,192 USER RAM (IN BYTES) 512
SERIAL COMMUNICATIONS INTERFACE MODULE (SCI)
2-CHANNEL TIMER/PWM MODULE (TPM)
TPMCH1 TCLK PTB0/IRQ/TCLK PTB1/RESET PTB2/BKGD/MS PTB3/BLMS
MODULE (MTIM) MULTI-PURPOSE CLOCK GENERATOR (MCG) VSSOSC VDD VSS LOW-POWER OSCILLATOR SYSTEM VOLTAGE REGULATOR 16-BIT Cyclic Redundancy Check Generator MODULE (CRC) EXTAL XTAL
PORT B
Bootloader ROM (IN BYTES) 4096
8-BIT MODULO TIMER
PTB4/XTAL PTB5/EXTAL
VUSB33
USB 3.3 V VOLTAGE REGULATOR REAL-TIME COUNTER (RTC)
NOTES: 1. Port pins are software configurable with pullup device if input port. 2. Pin contains software configurable pullup/pulldown device if IRQ is enabled (IRQPE = 1). Pulldown is enabled if rising edge detect is selected (IRQEDG = 1). 3. IRQ does not have a clamp diode to VDD. IRQ must not be driven above VDD. 4. RESET contains integrated pullup device if PTB1 enabled as reset pin function (RSTPE = 1). 5. Pin contains integrated pullup device. 6. When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used to reconfigure the pullup as a pulldown device.
Figure 1. MC9S08JS16 Series Block Diagram
MC9S08JS16 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 3
Pin Assignments
2
Pin Assignments
Table 1. Pin Availability by Package Pin-Count
Pin Number (Package) 24 (QFN) 20 (SOIC) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 4 5 6 7 8 -- 9 10 11 12 13 -- 14 15 16 17 18 -- 19 20 1 2 3 -- NC PTA5 NC PTA6 PTA7 PTB4 PTB5 KBIP6 KBIP7 XTAL EXTAL VSSOSC RxD TxD KBIP5 NC VSS USBDN USBDP VUSB33 TPMCH1 <-- Lowest Port Pin PTB0 PTB1 PTB2 PTB3 PTA0 NC PTA1 PTA2 PTA3 PTA4 KBIP1 KBIP2 KBIP3 KBIP4 MISO MOSI SPSCK SS VDD KBIP0 BKGD Priority Alt 1 IRQ --> Highest Alt 2 TCLK RESET MS BLMS TPMCH0
This section shows the pin assignments in the packages available for the MC9S08JS16 series.
MC9S08JS16 Series MCU Data Sheet, Rev. 4 4 Freescale Semiconductor
Pin Assignments
24 23
PTB0/IRQ/TCLK 1 PTB1/RESET 2 PTB2/BKGD/MS 3 PTB3/BLMS 4 PTA0/KBIP0/TPMCH0 5 NC 6
VSSOSC
NC
22
21
PTA7/KBIP7/TxD
PTB5/EXTAL
PTB4/XTAL
20
PTA6/KBIP6/RxD
19 18 NC 17 PTA5/KBIP5/TPMCH1 16 VUSB33
24-Pin QFN 15 USBDP 14 USBDN 7
PTA1/KBIP1/MISO
13 VSS 8
PTA2/KBIP2/MOSI
9
PTA3/KBIP3/SPSCK
10
PTA4/KBIP4/SS
11
VDD
12
NC
20 19 18 17 16 15 14 13 12 11
Figure 2. MC9S08JS16 Series in 24-QFN Package
PTB4/XTAL PTB5/EXTAL VSSOSC PTB0/IRQ/TCLK PTB1/RESET PTB2/BKGD/MS PTB3/BLMS PTA0/KBIP0/TPMCH0 PTA1/KBIP1/MISO PTA2/KBIP2/MOSI
1 2 3 4 5 6 7 8 9 10
PTA7/KBIP7/TxD PTA6/KBIP6/RxD PTA5/KBIP5/TPMCH1 VUSB33 USBDP USBDN VSS VDD PTA4/KBIP4/SS PTA3/KBIP3/SPSCK
Figure 3. MC9S08JS16 Series in 20-pin SOIC Package
MC9S08JS16 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 5
Electrical Characteristics
3
3.1
Electrical Characteristics
Parameter Classification
This chapter contains electrical and timing specifications.
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 2. Parameter Classifications
P C T Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations.
D
NOTE The above classifications are used in the column labeled "C" in applicable tables of this data sheet.
3.2
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the limits specified in Table 3 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD).
Table 3. Absolute Maximum Ratings
Rating Supply voltage Input voltage Instantaneous maximum current (applies to all port pins)1, 2, 3 Maximum current into VDD Storage temperature Maximum junction temperature Single pin limit Symbol VDD VIn ID IDD Tstg TJ Value 2.7 to 5.5 -0.3 to VDD + 0.3 25 120 -55 to 150 150 Unit V V mA mA C C
MC9S08JS16 Series MCU Data Sheet, Rev. 4 6 Freescale Semiconductor
Electrical Characteristics
1
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to VSS and VDD. 3 Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low which would reduce overall power consumption.
3.3
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than being controlled by the MCU design. In order to take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.
Table 4. Thermal Characteristics
Rating Operating temperature range (packaged) Thermal resistance 1,2,3,4 24-pin QFN 1s 2s2p 20-pin SOIC 1s 2s2p
1
Symbol TA
Value TL to TH -40 to 85
Unit C
JA
92 33 86 58
C/W
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance 2 Junction to Ambient Natural Convection 3 1s -- Single layer board, one signal layer 4 2s2p -- Four layer board, 2 signal and 2 power layers
The average chip-junction temperature (TJ) in C can be obtained from:
TJ = TA + (PD x JA) Eqn. 1
where: TA = Ambient temperature, C JA = Package thermal resistance, junction-to-ambient, C/W
MC9S08JS16 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 7
Electrical Characteristics
PD = Pint + PI/OPint = IDD x VDD, Watts -- chip internal power PI/O = Power dissipation on input and output pins -- user determined For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is:
PD = K / (TJ + 273C) Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = PD x (TA + 273C) + JA x (PD)2 Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA.
3.4
Electrostatic Discharge (ESD) Protection Characteristics
Although damage from static discharge is much less common on these devices than on early CMOS circuits, normal handling precautions must be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. This device was qualified to AEC-Q100 Rev E. A device is considered to have failed if, after exposure to ESD pulses, the device no longer meets the device specification requirements. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.
Table 5. ESD Protection Characteristics
Parameter ESD Target for Machine Model (MM) -- MM circuit description ESD Target for Human Body Model (HBM) -- HBM circuit description Symbol VTHMM VTHHBM Value 200 2000 Unit V V
3.5
DC Characteristics
This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various operating modes.
Table 6. DC Characteristics
Num C 1 Operating voltage2 Parameter Symbol -- Min 2.7 Typical1 -- Max 5.5 Unit V
MC9S08JS16 Series MCU Data Sheet, Rev. 4 8 Freescale Semiconductor
Electrical Characteristics
Table 6. DC Characteristics (continued)
Num C Parameter Output high voltage -- Low drive (PTxDSn = 0) 5 V, ILoad = -2 mA 3 V, ILoad = -0.6 mA 5 V, ILoad = -0.4 mA 3 V, ILoad = -0.24 mA Output high voltage -- High drive (PTxDSn = 1) 5 V, ILoad = -10 mA 3 V, ILoad = -3 mA 5 V, ILoad = -2 mA 3 V, ILoad = -0.4 mA Output low voltage -- Low drive (PTxDSn = 0) 5 V, ILoad = 2 mA 3 V, ILoad = 0.6 mA 5 V, ILoad = 0.4 mA 3 V, ILoad = 0.24 mA Output low voltage -- High drive (PTxDSn = 1) 5 V, ILoad = 10 mA 3 V, ILoad = 3 mA 5 V, ILoad = 2 mA 3 V, ILoad = 0.4 mA Output high current -- Max total IOH for all ports 4 P Output low current -- Max total IOL for all ports 5 6 7 8 9 10 11 12 13 14 15 16 17 P P Input high voltage; all digital inputs P Input low voltage; all digital inputs P Input hysteresis; all digital inputs P Input leakage current; input only pins P Internal pullup resistors4 P Internal pulldown resistors5 Internal pullup resistor to USBDP (to VUSB33) C C Input capacitance; all non-supply pins C RAM retention voltage P POR rearm voltage D POR rearm time Idle Transmit RPUPD CIn VRAM VPOR tPOR 900 1425 -- 0.6 0.9 10
3 3
Symbol
Min VDD - 1.5 VDD - 1.5 VDD - 0.8 VDD - 0.8 VDD - 1.5 VDD - 1.5 VDD - 0.8 VDD - 0.8 1.5 1.5 0.8 0.8 1.5 1.5 0.8 0.8
Typical1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.1 0.1 45 45 -- -- -- 1.0 1.4 --
Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 100 60 100 60 -- 0.35 x VDD -- 1 1 65 65 1575 3090 8 -- 2.0 --
Unit
2
P
VOH
V
3
P
VOL
V
5V 3V 5V 3V
IOHT
-- -- -- -- 0.65 x VDD -- 0.06 x VDD -- -- 20 20
mA
IOLT VIH VIL Vhys |IIn| |IOZ| RPU RPD
mA
V mV A A k k k pF V V s
P High Impedance (off-state) leakage current
MC9S08JS16 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 9
Electrical Characteristics
Table 6. DC Characteristics (continued)
Num C Parameter Low-voltage detection threshold -- high range VDD falling VDD rising Low-voltage detection threshold -- low range VDD falling VDD rising Low-voltage warning threshold -- high range 1 VDD falling VDD rising Low-voltage warning threshold -- high range 0 VDD falling VDD rising Low-voltage warning threshold low range 1 VDD falling VDD rising Low-voltage warning threshold -- low range 0 VDD falling VDD rising Low-voltage inhibit reset/recover hysteresis 24
1 2
Symbol
Min
Typical1
Max
Unit
18
P
VLVD1
3.9 4.0
4.0 4.1
4.1 4.2
V
19
P
VLVD0
2.48 2.54
2.56 2.62
2.64 2.70
V
20
C
VLVW3
4.5 4.6
4.6 4.7
4.7 4.8
V
21
P
VLVW2
4.2 4.3
4.3 4.4
4.4 4.5
V
22
P
VLVW1
2.84 2.90
2.92 2.98
3.00 3.06
V
23
C
VLVW0
2.66 2.72 -- --
2.74 2.80 100 60
2.82 2.88 -- --
V
T
5V 3V
Vhys
mV
Typical values are based on characterization data at 25 C unless otherwise stated. Operating voltage with USB enabled can be found in Section 3.11, "USB Electricals." 3 Measured with V = V In DD or VSS. 4 Measured with V = V . In SS 5 Measured with V = V . In DD
MC9S08JS16 Series MCU Data Sheet, Rev. 4 10 Freescale Semiconductor
Electrical Characteristics
IOH vs VDD-VOH (Low Drive) at VDD = 3 V
0.30 0.25 VDD-VOH (V) 0.20 0.15 0.10 0.05 0.00 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 -2.2 -2.4 -2.6 -2.8 -3 IOH (mA) -40C 25C 85C
Figure 4. Typical IOH (Low Drive) vs VDD-VOH at VDD = 3 V
IOH vs VDD-VOH (High Drive) at VDD = 3 V
0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 IOH (mA)
VDD-VOH (V)
-40C 25C 85C
Figure 5. Typical IOH (High Drive) vs VDD-VOH at VDD = 3 V
MC9S08JS16 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 11
Electrical Characteristics
IOH vs VDD-VOH (Low Drive) at VDD = 5 V
0.7 0.6 0.5 VOL (V) 0.4 0.3 0.2 0.1 0.0 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 -2.2 -2.4 -2.6 -2.8 -3 IOH(mA) -40C 25C 85C
Figure 6. Typical IOH (Low Drive) vs VDD-VOH at VDD = 5 V
IOH vs VDD-VOH (High Drive) at VDD = 5 V
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 IOH (mA)
VDD-VOH (V)
-40C 25C 85C
Figure 7. Typical IOH (High Drive) vs VDD-VOH at VDD = 5 V
MC9S08JS16 Series MCU Data Sheet, Rev. 4 12 Freescale Semiconductor
Electrical Characteristics
IOL vs VOL (Low Drive) at VDD = 5 V
0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00
-1 -1 .2 -1 .4 -1 .6 -1 .8 -2 0 -0 .2 -0 .4 -0 .6 -0 .8 -2 .2 -2 .4 -2 .6 -2 .8 -3
-40C 25C 85C
VOL (V)
IOL(mA)
Figure 8. IOL vs VOL (Low Drive) at VDD = 5 V
IOL vs VOL (High Drive) at VDD = 5 V
0.25 0.20 VOL (V) 0.15 0.10 0.05 0.00 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 IOL (mA) -40C 25C 85C
Figure 9. IOL vs VOL (High Drive) at VDD = 5 V
MC9S08JS16 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 13
Electrical Characteristics
IOL vs VOL (Low Drive) at VDD = 3 V
1.0 0.8 VOL (V) 0.6 0.4 0.2 0.0 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 -2.2 -2.4 -2.6 -2.8 -3 IOL (mA) -40C 25C 85C
Figure 10. IOL vs VOL (Low Drive) at VDD = 3 V
IOL vs VOL (High Drive) at VDD = 3 V
1.4 1.2 1.0 VOL (V) 0.8 0.6 0.4 0.2 0.0 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 IOL (mA) -40C 25C 85C
Figure 11. IOL vs VOL (High Drive) at VDD = 3 V
MC9S08JS16 Series MCU Data Sheet, Rev. 4 14 Freescale Semiconductor
Electrical Characteristics
3.6
Num 1
Supply Current Characteristics
Table 7. Supply Current Characteristics
C C Parameter Run supply current3 measured at (CPU clock = 2 MHz, fBus = 1 MHz, BLPE mode) Run supply current3 measured at (CPU clock = 48 MHz, fBus = 24 MHz, PEE mode, all module on) Stop2 mode supply current Symbol RIDD VDD (V) 5 3 5 RIDD 3 5 3 5 3 5 3 5 3 5 3 5 5 Typical1 1.03 0.83 19.93 18.74 1.36 1.18 1.50 1.31 300 300 106.7 95.6 5.6 5.3 1.5 273.3 Max2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- mA A A A A nA nA A A A A mA A Unit mA
2
P
3
P
S2IDD S3IDD ISRTC ISLVD ISOSC IUSBE ISUSP
4
P
Stop3 mode supply current, all module off RTC adder to stop2 or stop33, 25 C
5
P
6
P
LVD adder to stop3 (LVDE = LVDSE = 1) Adder to stop3 for oscillator enabled4 (ERCLKEN =1 and EREFSTEN = 1) USB module enable USB suspend current5
7 8 9
1 2 3 4 5
P T T
current6
6
Typicals are measured at 25 C. See Figure 12 through Figure 10 for typical curves across voltage/temperature. Values given here are preliminary estimates prior to completing characterization. Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait mode. Wait mode typical is 560 A at 5 V and 422 A at 3 V with fBus = 1 MHz. Values given under the following conditions: low range operation (RANGE = 0), low power mode (HGO = 0). Here USB module is enabled and clocked at 48 MHz (USBEN = 1, USBVREN =1, USBPHYEN = 1 and USBPU = 1), and D+ and D- pulled down by two 15.1 k resisters independently. The current consumption may be much higher when the packets are being transmitted through the attached cable. MCU enters stop3 mode, USB bus in idle state. The USB suspend current will be dominated by the D+ pullup resister.
MC9S08JS16 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 15
Electrical Characteristics
Typical Run IDD for PEE,FBE & BLPE
25.000 20.000 15.000 10.000 5.000 0.000 2.5 3 3.5 4 VDD(V) 4.5 5
IDD vs. VDD
PEE,48MHz Core FBE,8MHz Core BLPE,2MHz Core
IDD(mA)
5.5
Figure 12. Typical Run IDD for PEE, FBE and BLPE Modes (IDD vs. VDD)
MC9S08JS16 Series MCU Data Sheet, Rev. 4 16 Freescale Semiconductor
Electrical Characteristics
3.7
Num C
External Oscillator (XOSC) Characteristics
Table 8. Oscillator Electrical Specifications (Temperature Range = -40 to 85C Ambient)
Rating Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) Low range (RANGE = 0) High range (RANGE = 1) FEE or FBE mode2 High range (RANGE = 1) PEE or PBE mode3 High range (RANGE = 1, HGO = 1) BLPE mode High range (RANGE = 1, HGO = 0) BLPE mode Symbol flo fhi-fll fhi-pll fhi-hgo fhi-lp C1, C2 RF Min 32 1 1 1 1 Typ1 -- -- -- -- -- Max 38.4 5 16 16 8 Unit kHz MHz MHz MHz MHz
1
C
2 3
-- Load capacitors -- Feedback resistor Low range (32 kHz to 38.4 kHz) High range (1 MHz to 16 MHz)
See crystal or resonator manufacturer's recommendation. -- -- -- -- -- -- -- -- 10 1 0 100 0 0 0 0 200 400 5 15 -- -- -- -- -- -- -- -- 0 10 20 -- -- -- -- 5 16 40 M
4
Series resistor Low range, low gain (RANGE = 0, HGO = 0) Low range, high gain (RANGE = 0, HGO = 1) High range, low gain (RANGE = 1, HGO = 0) -- High range, high gain (RANGE = 1, HGO = 1) 8 MHz 4 MHz 1 MHz Crystal start-up time4 Low range, low gain (RANGE = 0, HGO = 0) Low range, high gain (RANGE = 0, HGO = 1) High range, low gain (RANGE = 1, HGO = 0)5 High range, high gain (RANGE = 1, HGO = 1)5 Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) FEE or FBE mode2 PEE or PBE mode3 BLPE mode
RS
k
5
T
t
t CSTL-LP CSTL-HGO t CSTH-LP
t CSTH-HGO
-- -- -- -- 0.03125 1 0
ms
6
1 2
T
fextal
MHz
Typical data was characterized at 3.0 V, 25 C or is recommended value. When MCG is configured for FEE or FBE mode, input clock source must be divided using RDIV to within the range of 31.25 kHz to 39.0625 kHz. 3 When MCG is configured for PEE or PBE mode, input clock source must be divided using RDIV to within the range of 1 MHz to 2 MHz. 4 This parameter is characterized and not tested on each device. Proper PC board layout procedures must be followed to achieve specifications. 5 4 MHz crystal.
MCU EXTAL XTAL RS
RF
C1
Crystal or Resonator
C2
MC9S08JS16 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 17
Electrical Characteristics
3.8
Num C 1 2 3 4 5 6 7 8
MCG Specifications
Table 9. MCG Frequency Specifications (Temperature Range = -40 to 85C Ambient)
Rating Symbol fint_ut fint_t tirefst fdco_ut fdco_t fdco_res_t fdco_res_t fdco_t fdco_t tfll_acquire tpll_acquire CJitter fvco fpll_ref fpll_jitter_2ms fpll_jitter_625ns Dlock Dunl tfll_lock tpll_lock floc_low floc_high Min 25 31.25 -- 25.6 32 -- -- -- Typical 32.7 -- 60 33.48 -- 0.1 0.2 0.5 -1.0 0.5 -- -- 0.02 -- -- 0.5904 0.5664 -- -- -- -- -- -- Max 41.66 39.0625 100 42.66 40 0.2 0.4 2 1 1 1 0.2 55.0 2.0 -- -- 2.98 5.97 tfll_acquire+
1075(1/fint_t)
Unit kHz kHz s MHz MHz %fdco %fdco %fdco %fdco ms ms %fdco MHz MHz % % % % s s kHz kHz
C Average internal reference frequency -- untrimmed P Average internal reference frequency -- trimmed T Internal reference startup time C DCO output frequency range -- untrimmed P DCO output frequency range -- trimmed Resolution of trimmed DCO output frequency at C fixed voltage and temperature (using FTRIM) C P Resolution of trimmed DCO output frequency at fixed voltage and temperature (not using FTRIM) Total deviation of trimmed DCO output frequency over voltage and temperature
9 10 11 12 13 14 15 16 17 18 19 20 21 22
1
Total deviation of trimmed DCO output frequency C over fixed voltage and temperature range of 0-70 C C FLL acquisition time1 D PLL acquisition time2 Long term Jitter of DCO output clock (averaged over C 2ms interval)3 D VCO operating frequency D PLL reference frequency range T Long term accuracy of PLL output clock (averaged over 2 ms) tolerance6
-- -- -- -- 7.0 1.0 -- -- 1.49 4.47 -- -- (3/5) x fint (16/5) x fint
T Jitter of PLL output clock measured over 625 ns5 D Lock entry frequency D Lock exit frequency D Lock time -- FLL D Lock time -- PLL D D Loss of external clock minimum frequency -- RANGE = 0 Loss of external clock minimum frequency -- RANGE = 1 tolerance7
tpll_acquire+
1075(1/fpll_ref)
-- --
This specification applies any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 2 This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
MC9S08JS16 Series MCU Data Sheet, Rev. 4 18 Freescale Semiconductor
Electrical Characteristics
3
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval. 4 Jitter measurements are based upon a 48 MHz clock frequency. 5 625 ns represents 5 time quanta for CAN applications, under worst case conditions of 8 MHz CAN bus clock, 1 Mbps CAN bus speed, and 8 time quanta per bit for bit time settings. 5 time quanta is the minimum time between a synchronization edge and the sample point of a bit using 8 time quanta per bit. 6 Below Dlock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG will not enter lock. But if the MCG is already in lock, then the MCG may stay in lock.
7
Below Dunl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock.
3.9
AC Characteristics
This section describes AC timing characteristics for each peripheral system.
3.9.1
Num 1 2 3 4 5 6 C D D D D D D
Control Timing
Figure 13. Control Timing
Parameter Bus frequency (tcyc = 1/fBus) Internal low-power oscillator period External reset pulse (tcyc = 1/fSelf_reset) Reset low drive Active background debug mode latch setup time Active background debug mode latch hold time IRQ pulse width Asynchronous path2 Synchronous path3 KBIPx pulse width Asynchronous path2 Synchronous path3 Port rise and fall time (load = 50 pF)4 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) width2 Symbol fBus tLPO textrst trstdrv tMSSU tMSH tILIH, tIHIL Min DC 700 1.5 x tSelf_reset 66 x tcyc 25 25 Typical1 -- -- -- -- -- -- Max 24 1300 -- -- -- -- Unit MHz s ns ns ns ns
7
D
100 1.5 x tcyc 100 1.5 x tcyc -- --
--
--
ns
8
D
tILIH, tIHIL
--
--
ns
9
1 2
C
tRise, tFall
3 30
-- --
ns
Typical values are based on characterization data at VDD = 5.0 V, 25 C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to override reset requests from internal sources. 3 This is the minimum pulse width guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 4 Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range -40C to 85C.
MC9S08JS16 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 19
Electrical Characteristics
textrst RESET PIN
Figure 14. Reset Timing
tIHIL IRQ/KBIPx
IRQ/KBIPx tILIH
Figure 15. IRQ/KBIPx Timing
3.9.2
Timer/PWM (TPM) Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 10. TPM Input Timing
Num 1 2 3 4 5 C D D D D D Function External clock frequency External clock period External clock high time External clock low time Input capture pulse width Symbol fTPMext tTPMext tclkh tclkl tICPW Min dc 4 1.5 1.5 1.5 Max fBus/4 -- -- -- -- Unit MHz tcyc tcyc tcyc tcyc
tTPMext tclkh
TPMxCLK tclkl
Figure 16. Timer External Clock
MC9S08JS16 Series MCU Data Sheet, Rev. 4 20 Freescale Semiconductor
Electrical Characteristics
tICPW TPMxCHn
TPMxCHn tICPW
Figure 17. Timer Input Capture Pulse
3.10
SPI Characteristics
Table 11 and Figure 18 through Figure 21 describe the timing requirements for the SPI system.
MC9S08JS16 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 21
Electrical Characteristics
Table 11. SPI Electrical Characteristic
Num1 C Characteristic2 Operating frequency3 1 D Cycle time 2 D Enable lead time 3 D Enable lag time 4 D Clock (SPSCK) high time 5 D Clock (SPSCK) low time 6 D Data setup time (inputs) 7 D Data hold time (inputs) 8 9 10 11 D D D D Data hold time (outputs) 12
1
Symbol
Min
Typical
Max
Unit
Master Slave Master Slave Master Slave Master Slave Master Slave Master Slave Master Slave Master Slave Access time, slave4 Disable time, slave5 Data setup time (outputs) Master Slave Master Slave
fop fop tSCK tSCK tLead tLead tLag tLag
fBus/2048DC
-- -- -- -- 1/2 1/2 1/2 1/2 1/2 tSCK 1/2 tSCK 1/2 tSCK 1/2 tSCK -- -- -- -- -- -- -- -- -- --
fBus/2 fBus/4 2048 -- -- -- -- -- -- -- -- -- -- -- -- -- 40 40 25 25 -- --
Hz
2 4 -- -- -- -- -- 1/2 tSCK - 25 -- 1/2 tSCK - 25 30 30 30 30 -- -- -- -- -10 -10
tcyc
tSCK
tSCK
tSCKH
ns
tSCKL
ns
tSI(M) tSI(S) tHI(M) tHI(S) tA tdis tSO tSO tHO tHO
ns
ns ns ns ns
D
ns
Refer to Figure 18 through Figure 21. All timing is shown with respect to 20% VDD and 80% VDD, unless noted; 50 pF load on all SPI pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output pins. 3 The maximum frequency is 8 MHz when input filter on SPI pins is disabled. 4 Time to data active from high-impedance state. 5 Hold time to high-impedance state.
2
MC9S08JS16 Series MCU Data Sheet, Rev. 4 22 Freescale Semiconductor
Electrical Characteristics
SS1 (OUTPUT) 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) 6 MISO (INPUT) MSB IN2 10 MOSI (OUTPUT) MSB OUT2 7 BIT 6 . . . 1 10 BIT 6 . . . 1 LSB OUT LSB IN 12 1 5 4 3
5 4
NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 18. SPI Master Timing (CPHA = 0)
SS(1) (OUTPUT) 1 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) MISO (INPUT) 10 MOSI (OUTPUT) MSB OUT(2) 5 4 5 4 6 7 MSB IN(2) BIT 6 . . . 1 12 BIT 6 . . . 1 LSB OUT LSB IN 3
NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 19. SPI Master Timing (CPHA = 1)
MC9S08JS16 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 23
Electrical Characteristics
SS (INPUT) 1 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 MISO (OUTPUT) SLAVE 6 MOSI (INPUT)
NOTE:
3 5
4
5 4 10 MSB OUT 7 MSB IN BIT 6 . . . 1 LSB IN BIT 6 . . . 1 12 SLAVE LSB OUT SEE NOTE 9
1. Not defined but normally MSB of character just received
Figure 20. SPI Slave Timing (CPHA = 0)
SS (INPUT) 1 2 SCK (CPOL = 0) (INPUT) SCK (CPOL = 1) (INPUT) MISO (OUTPUT) SEE NOTE 8 MOSI (INPUT) 5 4 5 4 10 SLAVE 6 MSB IN MSB OUT 7 BIT 6 . . . 1 LSB IN 12 BIT 6 . . . 1 SLAVE LSB OUT 9 3
NOTE: 1. Not defined but normally LSB of character just received
Figure 21. SPI Slave Timing (CPHA = 1)
3.11
Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply.
MC9S08JS16 Series MCU Data Sheet, Rev. 4 24 Freescale Semiconductor
Electrical Characteristics
Table 12. Flash Characteristics
Num 1 2 3 4 5 6 7 8 C D D D D P P P P Characteristic Supply voltage for program/erase Supply voltage for read operation Internal FCLK frequency2 Internal FCLK period (1/FCLK) Byte program time (random location)2 Byte program time (burst mode)2 Page erase time3 Mass erase time2 Program/erase endurance4 TL to TH = -40C to 85 C T = 25 C Data retention5 Symbol Vprog/erase VRead fFCLK tFcyc tprog tBurst tPage tMass Min 2.7 2.7 150 5 Typical1 -- -- -- -- 9 4 4000 20,000 Max 5.5 5.5 200 6.67 Unit V V kHz s tFcyc tFcyc tFcyc tFcyc
9
C
--
10,000 -- 15
-- 100,000 100
-- -- --
cycles
10
1 2
C
tD_ret
years
Typical values are based on characterization data at VDD = 5.0 V, 25 C unless otherwise stated. The frequency of this clock is controlled by a software setting. 3 These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 4 Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how Freescale Semiconductor defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile Memory. 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 C using the Arrhenius equation. For additional information on how Freescale Semiconductor defines typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory.
3.12
USB Electricals
The USB electricals for the S08USBV1 module conform to the standards documented by the Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit http://www.usb.org. If the Freescale S08USBV1 implementation requires additional or deviant electrical characteristics, this space would be used to communicate that information.
Table 13. Internal USB 3.3 V Voltage Regulator Characteristics
Symbol Regulator operating voltage Vreg output Vreg filter capacitor Vusb33 input with internal Vreg disabled Vregin Vregout Cusbreg Vusb33in Min 3.9 3 -- 3 Typical -- 3.3 100 3.3 Max 5.5 3.6 -- 3.6 Unit V V pF V
MC9S08JS16 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 25
Ordering Information
Table 14. External 3.3 V Voltage Regulator Supply for Vusb33 Pin
Symbol External 3.3 V regulator output current -- Min 39 Typical -- Max -- Unit mA
4
Ordering Information
This section contains ordering information for Device Numbering System. See below for an example of the device numbering system.
MC 9 S08 JS Status (MC = Fully qualified) Memory (9 = Flash-based) Core Family 16 (L) C XX Package designator (See Table 15) Temperature range (C = -40 C to 85 C) USB bootloader supported at 3.3 V Approximate memory size (in KB)
4.1
Package Information
Table 15. Package Descriptions
Package Type Quad Flat No-Leads Wide Body Small Outline Integrated Circuit Abbreviation QFN W-SOIC Designator FK WJ Case No. 1982-01 751D Document No. 98ARL10608D 98ASB42343B
Pin Count 24 20
4.2
Mechanical Drawings
This following pages contain mechanical specifications for MC9S08JS16 series package options. * 24-pin QFN (quad flat no-lead) * 20-pin W-SOIC (wide body small outline integrated circuit)
MC9S08JS16 Series MCU Data Sheet, Rev. 4 26 Freescale Semiconductor
How to Reach Us:
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FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2008-2009. All rights reserved. MC9S08JS16 Rev. 4 4/2009

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